This research investigation will use a single-bit full adder to develop a multiplier, which is a vital arithmetic operation in modern technology and will determine the outcome of the work presented in this paper. There have been several modern designs of multipliers, including the Vedic multiplier, the Wallace tree multiplier, the booth multiplier, and the approximation multiplier, all of which place a premium on the addition unit in order to reduce the arithmetic logic and improve processing performance. For this reason, the proposed work will use a truncated multiplier design. This is because a truncated multiplier can reduce the size of both the internal and external architecture of a given design by rounding, deleting, or truncating the LSB bits. In this case, the MSB bits will be truncated, and the result of an n-by-n multiplication will be presented at a single n-bit level. This proposed effort would use CMOS logic gate design to create entire adders with a 10-T transistor level and 45nm technology, demonstrating significant improvements in these metrics. The simulation results show that the proposed adder circuit employing the GDI method module reduces power consumption by 91.5%, reduces latency by 93.2%, and reduces the system's PDP by 91.64% compared to the state-of-the-art 65nm CMOS Technology. When operating at 100 KHz, Amp 0.5V, offset 2.5v, and input voltage 1. 8v, the 8-order FIR filter design wastes 0.7068 nW without degrading the filter frequency response or the signal-to-noise ratio (SNR) of recorded 8-bit Modulation signals. Improved space and power savings for CMOS VLSI Filters are made possible by our approximation adder technique.