Discrete Wavelet Transform (DWT) is wide used in signal and image processing applications. VLSI implementation of DWT architecture optimizing area, power and speed performances is carried out by design of customized architectures. In this paper, Distributive Arithmetic (DA) based algorithm is developed and a suitable architecture is designed considering symmetric property of filter coefficients. The improved method for DWT filter bank implementation occupies less than 1% of the total area required by direct implementation. The architecture is optimized for ASIC implementation and power dissipation is optimized. Power saving of 62% is achieved in implementing the design targeting 45nm technology. With low power filter bank design, DWT based signal and image processing applications can be implemented.