In recent decades the demands for high performance semiconductor designs has been emerging steadily. In particular the Multi-core platforms are growing in the design of System-on-Chips (SoCs). The large set wire interconnect in these multi core designs decides the overall system performance both in terms of energy efficiency and attainable speed of data transmission. But with the recent advancement in semiconductor industry with advanced transistor scaling the SoC level design includes more number of dedicated functional blocks in which convention FIFO based single cross bar enabled routers increases the power consumption. In many applications the excessive usage of cross bar restricts the applicability of Network on chip due to its power hungry statistical nature with associated complexity overhead. To mitigate these issues related to the existing NOC, in this paper optimal Finite state machine (FSM) controlled Multi cross bar routers are introduced for routing operation. As compared to conventional Routers in the proposed framework the path delay and associated power is significantly reduced and also avoid possible traffic congestions among routers. The performance metrics also includes asynchronous data transmission between IP blocks with least possible latency overhead