The optimisation of a 45 nm NMOS device is investigated by applying silicide layer on Poly-Silicon Gate. This approach is utilised to analyse the experimental data and get the best results. Silicides are generally chosen because of their appropriate electrical characteristics, such as low resistance, compatibility with silicon manufacturing processes, minimal to non-existent electro-migration, ease of dry etching, and good interaction with other materials. Silicide on the Poly-Si Gate electrode is used to reduce the Gate electrode resistance. The device is virtually fabricated with channel length of 45nm using ATHENA module of SILVACO and the electrical characteristics of the device are analysed using ATLAS module of SILVACO. There are various materials that can be used as Poly-cide i.e silicide on Poly-silicon. In this paper, the comparative analysis of silicide process to increase the conductivity of Poly-Si gate has been done. The four different materials are considered separately during the virtual fabrication of 45nm NMOS device. The platinum silicide has lowest OFF state leakage current equals to 6.06385nA after optimization approach