In recent days, reduced instructions play a vital role in the processor development. Reduced Instruction Set Computers (RISCs) are such instructions which provide offers to these applications. This project suggests using double precision to implement the programme and loading unit on 64-bit RISC processors. The characteristics of this processor are they operate at fast speed while using low power. The CPU is divided into three sections: the execution portion, the instruction decodes and fetch. By employing parallel architectures, floating point ALU with double-precision is proposed. The proposed architecture not only improves the speed, but also the precision. Design of each and every block is written using Verilog HDL and simulation results are observed