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ISSN 2063-5346
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DESIGN AND VERIFICATION OF 32-BIT RISC PROCESSORUSING VEDIC MULTIPLIER

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Amrutha Vani S 1 , Dr T Somassoundaram2
» doi: 10.48047/ecb/2023.12.Si8.785

Abstract

This paper introduces a 32-bit RISC processor designed with a unique Vedic multiplier, aiming for enhanced performance and speed. The architecture employs a simplified instruction set and features a hybrid adder optimized for space efficiency

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