This paper describes features of a network on infrastructure in System on Chips (SoCs) as traditional methods exhibit severe bottlenecks at intercommunication among processor elements. However, designing a NoC is highly complex due to a number of factors There are a number of issues concerning the performance metrics of system scalability, latency, power consumption, and signal integrity in routers. This paper discusses the memory unit in routers and proposes a more advanced memory structure.comparing the simulations and synthesis results to previous walls, guaranteed throughput. Comparing the simulation and synthesis results to provide works, guaranteed throughput predictable latency, and uniform network access are highly provided.